If an output driver for an integrated circuit has an output impedance that is mismatched to the characteristic impedance of the traces and interconnects that couple the integrated circuit to external devices, undesirable effects may occur such as jitter and signal reflections. Thus, it is conventional for an integrated circuit output driver to have some configurability so that it may be calibrated to the desired output impedance. To achieve this calibration, a conventional driver includes a pull-down section as well as a pull-up section for driving a data output signal. When such an output driver asserts the data output signal high, the pull-up section pulls the driver's output pad to a power supply voltage VDD. Conversely, when the output driver drives the data output signal low, the pull-down section discharges the driver's output pad to ground (VSS). Each section includes a plurality of legs, with a subset of the legs each including a calibration transistor. A calibration word for each section comprising a plurality of calibration bits controls the section's calibration transistors. The assertion of a calibration bit in the calibration word for the pull-down section causes the corresponding calibration transistor to switch on and conduct current from the output pad to VSS. Conversely, the assertion of a calibration bit in the calibration word for the pull-up section causes the corresponding calibration transistor to switch on and conduct charge from a power supply node to the output pad to charge its voltage to VDD. Since each leg has a corresponding resistor, the driving of current through the selected calibration transistors adjusts the output impedance.
Although the calibration transistors assist in the impedance matching, they also complicate the loading of the data output signal in the pull-up and pull-down sections. For example, FIG. 1 illustrates a conventional pull-down section 105 for an output driver 100. Pull-down section 105 functions to discharge an output pad 110 to ground in response to the assertion of a complement data output signal (nd). Conversely, the pull-up section (not illustrated) functions to charge output pad 110 to a power supply voltage VDD in response to the assertion of the data output signal.
A default leg in pull-down section 105 discharges output pad 110 to ground (VSS) through a resistor R in response to an NMOS data transistor M1 switching on when the complement data output signal nd is asserted. Each selectable leg also includes an NMOS data transistor M1 that conducts responsive to the assertion of the complement data output signal nd. But each selectable leg also includes an NMOS calibration transistor that will conduct only when the corresponding calibration bit is asserted. For example, a selectable leg 0 includes an NMOS calibration transistor M2 having a gate coupled through a transmission gate T1 to the complement data output signal nd. A calibration bit C0 controls transmission gate T1 so that transmission gate T1 closes when calibration bit C0 is asserted and opens when calibration bit C0 is de-asserted. Thus, in response to an assertion of both calibration bit C0 and the complement data output signal nd, selectable leg 0 discharges output pad 110 to ground through a resistor R1. Selectable leg 1 includes an NMOS calibration transistor M3 that discharges output pad 110 to ground through a resistor R2 in response to the assertion of the complement data output signal nd and a calibration bit C1 closing a transmission gate T2.
Before the manufacture in a foundry, one does not know the process corner for the resulting semiconductor substrate in which driver 100 is integrated. If driver 100 were manufactured with a fast process corner, transistor M1 in the default leg may function to sink sufficient current such that none of the calibration bits need be asserted. In other words, a fast corner output driver 100 may provide the desired output impedance without using any of the selectable legs. But at slower process corners, more and more of the selectable legs become necessary to produce the desired output impedance. At each slower process corner, one or more of the selectable legs are turned on through their assertion of their corresponding calibration bit. But notice the problem—the complement data output signal nd is subjected to more of a capacitive load through the various closed transmission gates at these slower process corners. In contrast, the complement data output signal nd is not loaded at the fast process corners. This is the converse of what is desired since the slower slew rates at the slower process corners are slowed down even more by the extra capacitive loading in the selectable legs.
Accordingly, there is a need in the art for impedance-calibrated output drivers with enhanced slew rate control.